Many processors operate according to a cycle whereby program instructions are fetched from memory, decoded, and dispatched to one or more functional units, which perform operations specified by the instructions. The processor may track pending instructions that have been dispatched and are awaiting execution by the functional units. For example, when the processor dispatches an instruction of execution, a record of the pending instruction (or transaction) may be stored in an instruction window until the functional unit indicates that all necessary operations for the instruction have been completed. Upon receipt of this acknowledgement, the processor clears the pending instruction from the instruction window. If new instructions are fetched, decoded, and dispatched while all functional units are busy processing other instructions, the processor queues the new instructions in the instruction window to await execution.
During building and testing of a new system (e.g., a new motherboard or system-on-chip), a system designer may wish to initiate an external debug event in order to halt the processor and place the processor in a debug state so that the internal state of the processor (e.g., the general purpose and system registers) can be viewed. In response to such an external debug event, the processor typically waits until all pending transactions have completed execution before entering the debug state.
However, there may be circumstances in which the processor is not able to complete an outstanding transaction, and the recipient of the pending transaction (e.g., the functional unit) does not reply with an appropriate acknowledgement (ACK) or negative acknowledgement (NACK) in response to the transaction initiated by the processor. As a result, the transaction remains pending indefinitely, a situation referred to herein as “processor hang.” If an external debug event is received while in this hung state, the processor fails to enter the debug state, since the processor continues to wait for completion of the hung transaction. Consequently, the internal state of the processor is not available to the user. Moreover, the processor may not contain necessary information regarding the cause of the hung state.
The above-described description is merely intended to provide a contextual overview of current techniques and is not intended to be exhaustive.